Semiconductor device having pair of transistors

ABSTRACT

A semiconductor device includes a plurality of groups of transistor elements which are formed on a single semiconductor chip, each group having a first pair of transistor elements which are arranged so as to be symmetrical about a point and a second pair of transistor elements which are arranged, in a direction perpendicular to a direction in which the first pair of transistor elements are arranged, so as to be symmetrical about the point. The first pair of transistor elements in all the plurality of groups are connected in parallel so that a first transistor is formed of the first pair of transistor elements, and the second pair of transistor elements in all the plurality of groups are connected in parallel so that a second transistor is formed of the second pair of transistor elements, the first transistor and the second transistor being paired.

The present application is a continuation application of U.S. patentapplication Ser. No. 08/184,665, filed Jan. 21, 1994, and now abandoned.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention generally relates to a semiconductor device, andmore particularly to a semiconductor device having a pair of transistorswhich should have the same electrical characteristic, such as adifferential amplifier.

(2) Description of the Related Art

FIG. 1 is an equivalent circuit diagram illustrating a conventionaldifferential amplifier. Referring to FIG. 1, a differential amplifier 1has an input stage 2 and an output stage 3. The input stage 2 comprisesa first pair of transistors Qa and Qb, a second pair of transistors Qcand Qd and a constant-current source J. The transistors Qa and Qb areso-called differential pair transistors (differential inputtransistors). Emitters of the differential pair transistors Qa and Qbare connected to each other and the constant-current source J isconnected to the emitters thereof. Collectors of the second pair oftransistors Qc and Qd are respectively connected to collectors of thefirst pair of transistors Qa and Qb so that the second pair oftransistors Qc and Qd function as a constant-current load of thedifferential pair transistors Qa and Qb. The second pair of transistorsQc and Qd form a current mirror circuit, and the transistors Qc and Qdare so-called current mirror transistors. Bases of the differential pairtransistors Qa and Qb are connected to input terminals (an invertinginput terminal and a non-inverting terminal) 5 and 6 between whichsignals are supplied. Emitters of the current mirror transistors Qc andQd are connected to a power source terminal 4, and the output unit 3 isconnected to the collectors of the transistors Qb and Qd so that avoltage in accordance with a voltage of a signal supplied between theinput terminals 5 and 6 is output from an output terminal 7 thereof.

In the above differential amplifier, it is desired that no DC offsetvoltage be output from the output terminal 7 under a condition in whicha voltage between the input terminals 5 and 6 (the bases of thedifferential pair transistors Qa and Qb) is equal to zero. The DC offsetvoltage depends on the difference between forward drop characteristicsin base-emitter junctions of the differential pair transistors Qa andQb. Thus, both the differential pair transistor Qa and Qb are generallymade on a single semiconductor chip so as to have the same electricalcharacteristics (including the forward drop characteristics in thebase-emitter junctions).

However, it is difficult to obtain differential pair transistors havingexactly the same electrical characteristics. Due to the variations ofplane shapes of elements of each transistor which variation is caused bythe mask resolution and due to the variation of a semiconductorcharacteristic (a resistivity) in a direction parallel to a surface of asemiconductor chip which variation is caused by irregularities in adiffusion process, the electrical characteristic of each transistor isvaried.

It has been known that the above variation caused by the mask resolutioncan be reduced by increasing the size of each transistor in a directionparallel to the surface of the semiconductor chip. It has been alsoknown that the above variation caused by the irregularities in thediffusion process can be reduced by forming the differential pairtransistors as shown in FIGS. 2A and 2B.

Referring to FIG. 2A, each of the differential pair transistors Qa andQb is formed of two transistor elements. That is, a first transistor Qaout of the differential pair transistors Qa and Qb is formed oftransistor elements Q1 and Q4 which are connected to each other inparallel and a second transistor Qb out of the differential pairtransistors Qa and Qb is formed of transistor elements Q2 and Q3 whichare connected to each other in parallel. The above four transistors Q1,Q2, Q3 and Q4 are formed on a semiconductor chip so as to be arranged asshown in FIG. 2B. This arrangement of the transistors Q1, Q2, Q3 and Q4are often referred to as a common-centroid layout. Referring to FIG. 2B,the transistor elements Q1 and Q4 forming the first transistor Qa arearranged on a semiconductor chip so as to be symmetrical about a centerpoint O, and the transistor elements Q2 and Q3 forming the secondtransistor Qb are arranged on the semiconductor chip, in a directionperpendicular to a direction in which the transistor elements Q1 and Q4are arranged, so as to be symmetrical about the center point O.Furthermore, the transistor elements Qt and Q2 are symmetrical about ay-axis, the transistors Q3 and Q4 are symmetrical about the y-axis, thetransistors Q1 and Q3 are symmetrical about an x-axis perpendicular tothe y-axis, and the transistors Q2 and Q4 are symmetrical about thex-axis.

In the differential pair transistors Qa and Qb having the aboveconstruction in accordance with the common-centroid layout as shown inFIG. 2B, the location of the transistor element Q1 is the same as thoseof the transistor elements Q2 and Q3 respectively in directions of they-axis and the x-axis, and the location of the transistor element Q4 isthe same as those of the transistor elements Q2 and Q3 respectively indirections of the x-axis and the y-axis. Thus, even if the semiconductorchip has the gradient of the resistivity in a direction parallel to thex-axis, the electrical characteristics of the transistor elements Q1 andQ4 are respectively similar to those of the transistors Q3 and Q2. Inaddition, even if the semiconductor chip has the gradient of theresistivity in a direction parallel to the y-axis, the electricalcharacteristics of the transistor elements Q1 and Q4 are respectivelysimilar to those of the transistors Q2 and Q3. As a result, even if thesemiconductor chip has the gradient of the resistivity in any direction,the electric characteristic of the first transistor Qa formed of thetransistors Q1 and Q4 is similar to that of the second transistor Qbformed of the transistors Q2 and Q3.

However, the equality of the differential transistors Qa and Qb in theelectric characteristic is not sufficient to further reduce the offsetvoltage in the differential amplifier 1.

SUMMARY OF THE INVENTION

Accordingly, a general object of the present invention is to provide anovel and useful semiconductor device having a pair of transistors whichshould have the same electrical characteristic, in which semiconductordevice the disadvantages of the aforementioned prior art are eliminated.

A more specific object of the present invention is to provide asemiconductor device having a pair of transistors in which the equalitythereof in the electrical characteristic can be improved.

The above objects of the present invention are achieved by asemiconductor device comprising: plurality of groups of transistorelements which are formed on a single semiconductor chip, each grouphaving a first pair of transistor elements which are arranged so as tobe symmetrical about a point and a second pair of transistor elementswhich are arranged, in a direction perpendicular to a direction in whichthe first pair of transistor elements are arranged, so as to besymmetrical about the point; means for connecting the first pair oftransistor elements in all the plurality of groups in parallel so that afirst transistor is formed of the first pair of transistor elements; andmeans for connecting the second pair of transistor elements in all theplurality of groups in parallel so that a second transistor is formed ofthe second pair of transistor elements, the first transistor and thesecond transistor being paired.

According to the present invention, a pair of the transistors are formedof a plurality of groups of transistor elements which are formed on asingle semiconductor chip, each group having a first pair of transistorelements which are arranged so as to be symmetrical about a point and asecond pair of transistor elements which are arranged in a directionperpendicular to a direction in which the first pair of transistorelements are arranged, so as to be symmetrical about the point. Thus,even if the semiconductor characteristic of the single semiconductorchip has the gradient in any direction, the equality of the transistorswhich are paired can be improved.

Additional objects, features and advantages of the present inventionwill become apparent from the following detailed description when readin conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an equivalent circuit diagram illustrating a differentialamplifier having a conventional pair of transistors.

FIG. 2A is an equivalent circuit diagram illustrating a conventionaldifferential pair transistors included in the differential amplifiershown in FIG. 1.

FIG. 2B is a diagram illustrating the arrangement of transistor elementsforming the conventional differential pair transistors on asemiconductor chip.

FIG. 3A is an equivalent circuit diagram illustrating a differentialamplifier having a pair of transistors according to an embodiment of thepresent invention.

FIG. 3B is a diagram illustrating a structure of the pair of transistorsshown in FIG. 3A.

FIG. 4 is a diagram illustrating the arrangement of transistor elementsforming each of sets of transistor elements shown in FIG. 3B.

FIG. 5 is an equivalent circuit diagram of another embodiment of thepresent invention.

FIG. 6 is an equivalent circuit diagram illustrating a differentialamplifier formed of MOS transistor elements.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

It has been experimentally known that the electrical characteristics ofelements, such as transistors, which are formed close to each other on asemiconductor chip are in a normal distribution. Assuming that thestandard deviation of the normal distribution of electriccharacteristics of the elements close to each other on the semiconductorchip and a center value in the normal distribution are respectivelyrepresented by σ_(0i) and X_(o), the standard deviation σ of adistribution of electrical characteristics of groups of elements, eachgroup having n elements connected to each other in parallel isrepresented by

    σ=σ.sub.0 /√n.

Thus, the larger the number (n) of elements included in each group, thesmaller the standard deviation σ. That is, the variation of theelectrical characteristics of the groups of elements formed on thesemiconductor chip can be reduced. The present invention is based on theabove viewpoint.

A description will now be given, with reference to FIGS. 3A, 3B and 4,of an embodiment of the present invention.

In FIG. 3A, which shows a differential amplifier, those parts which arethe same as those shown in FIG. 1 are given the same reference numbers.Referring to FIG. 3A, the differential amplifier has the differentialpair transistors Qa and Qb respectively coupled to the input terminals 5and 6, the current mirror transistors Qc and Qd coupled to the powersource terminal 4 and the output stage 3 coupled to the output terminal7 all of which are connected to each other in the same manner as thosein the conventional differential amplifier shown in FIG. 1. The firsttransistor Qa from the differential pair transistors Qa and Qb has fiftytransistor elements Q11, Q14, Q21, Q24, . . . , Q251 and Q254 which areconnected to each other in parallel. The second transistor Qb from thedifferential pair transistors Qa and Qb has also fifty transistorelements Q12, Q13, Q22, Q23, . . . , Q252 and Q253 which are connectedto each other in parallel.

All the transistor elements forming the differential pair transistors Qaand Qb are formed on a single semiconductor chip so as to be arrangedand connected to each other as shown in FIG. 3B. Referring to FIG. 3B,twenty five transistor areas Sjk (j=1,2, . . . and 5, and k=1,2, . . .and 5) are arranged in a 5×5 matrix on the semiconductor device. Each ofthe transistor areas Sjk imaginarily has a center point Oi positioned atthe center thereof. On each of the twenty five transistor areas Sjk,four transistor elements Qi1, Q12, Qi3 and Qi4 are formed so as to bearranged in accordance with the common-centroid layout as describedabove. That is, on each of the transistor areas Sjk, two transistorelements Qi1 and Qi4 included in the first transistor Qa from thedifferential pair transistor Qa and Qb are arranged so as to besymmetrical about the center point Oi, and other two transistor elementsQi2 and Qi3 included in the second transistor Qb are arranged, in adirection perpendicular to a direction in which the above two transistorelements Qi1 and Qi4 are arranged, so as to be symmetrical about thecenter point Oi. The transistor elements Qi1 and Qi4 (the subscriptnumber i is varied from 1 to 25) on the respective transistor areas Sjk(the subscript numbers j and k are respectively varied from 1 to 5) areconnected in parallel, and the transistor elements Qi2 and Qi3 on therespective transistor areas Sjk are connected in parallel.

Detailed arrangement and connection of the four transistor elements Qi1,Qi2, Qi3 and Qi4 on each of the transistor areas Sjk are shown in FIG.4. Referring to FIG. 4, the transistor elements Qi1, Qi2, Qi3 and Qi4respectively have emitter areas E1, E2, E3 and E4, collector areas C1,C2, C3 and C4 and base areas B1, B2, B3 and B4. On the transistorelements Qi1 and Qi4 which are arranged so as to be symmetrical aboutthe center point Oi, the emitter area E1, the collector area C1 and thebase areas B1 are respectively symmetrical to the emitter area E4, thecollector area C4 and the base area B4 about the center point Oi. Inaddition, on the transistor elements Qi2 and Qi3 which are arranged soas to be symmetrical about the center point Oi, the emitter area E2, thecollector area C2 and the base area B2 are respectively symmetrical tothe emitter area E3, the collector area C3 and the base area B3 aboutthe center point Oi. The transistor elements Qi1 and Qi4 arerespectively symmetrical to the transistor elements Qi3 and Qi2 aboutthe x-axis, and are respectively symmetrical to the transistor elementsQi2 and Qi3 about the y-axis.

The transistor elements Qi1, Qi2, Qi3 and Qi4 are connected to eachother as shown by dotted lines in FIG. 4. That is, the emitter areas E1,E2, E3 and E4 of all the transistor elements Qi1, Qi2, Qi3 and Qi4 areconnected by a line L_(E), the collector areas C1 and C4 of thetransistor elements Qi1 and Qi4 are connected by a line L_(C1), thecollector areas C2 and C3 of the transistor elements Qi2 and Qi3 areconnected by a line L_(C2) to each other, the base areas B1 and B4 ofthe transistor elements Qi1 and Qi4 are connected by a line L_(B1), andthe base areas B2 and B3 of the transistor elements Qi2 and Qi3 areconnected by a line L_(B2). Lines L_(E) of all the transistor areas areconnected to each other and to the constant power source J. Lines L_(C1)of all the transistor areas are connected to each other and to thecollector of the transistor Qc, and lines L_(C2) of all the transistorareas are connected to each other and to the collector of the transistorQd. Furthermore, lines L_(B1) of all the transistor areas are connectedto each other and to the input terminal 5, and lines L_(b2) of all thetransistor areas are connected to each other and to the input terminal6. As a result, the transistor elements Q11, Q14, Q21, Q24, . . . , Q251and Q254 forming the first transistor Qa and the transistor elementsQ12, Q13, Q22, Q23, . . . , Q252 and Q253 forming the second transistorQb are connected as shown in FIGS. 3A and 3B.

In FIG. 3B, continuous lines coupling transistor elements indicates thatthe transistor elements are connected in parallel, and a chain lineindicates that emitters of the transistor elements forming the firsttransistor Qa are connected to emitters of the transistor elementsforming the second transistor Qb.

According to the above embodiment of the present invention, in each ofthe transistor areas Sjk, even if the semiconductor chip (asemiconductor substrate) has the gradient of the resistivity in anydirection, the electric characteristics of the differential pairtransistor are substantially equal to each other. In addition, sinceeach of the differential pair transistors Qa and Qb is formed of twentyfive pairs of transistor elements connected in parallel, thedistribution of the electrical characteristics of the differential pairtransistors formed on the single semiconductor chip has the standarddeviation σ₂₅ :

    σ.sub.25 =σ.sub.0 /√n=σ.sub.0 /5.

That is, the variation (the standard deviation of the distribution) ofthe electric characteristics of the differential pair transistors formedon the single semiconductor chip is reduced to a value which is onefifth of the conventional value.

Thus, the equality of the forward drop characteristics a h_(FE)characteristic and other electrical characteristics of the differentialpair transistors Qa and Qb can be improved, so that the DC offsetvoltage of the differential amplifier can be further reduced.

In the above embodiment, the transistor areas Sjk, on each of which fourtransistor elements are formed in accordance with the common-centroidlayout, may be arranged in mosaic instead of in the matrix.

A description will now be given, with reference to FIG. 5, of anotherembodiment of the present invention.

FIG. 5 shows a differential amplifier having the differential pairtransistors Qa and Qb, the current mirror transistors Qc and Qd, theconstant power source J and the output stage 3 in the same manner asthat shown in FIGS. 1 and 3A. In this embodiment, the differentialtransistors Qa and Qb are respectively formed of a group of transistorelements Q11, Q14, Q21, Q24, . . . , Qn1 and Qn4 connected to each otherin parallel and a group of transistor elements Q12, Q13, Q22, Q23, . . ., Qn2 and Qn3, in the same manner as that shown in FIGS. 3A and 3B.Furthermore, the current mirror transistors Qc and Qd are respectivelyformed of a group of transistor elements Q15, Q18, Q25, Q28, . . . , Qm5and Qm8 connected to each other in parallel and a group of transistorelements Q16, Q17, Q26, Q27, . . . , Qm6 and Qm7.

The transistor elements forming the current mirror transistors Qc and Qdare formed on a single semiconductor chip. On the single semiconductorchip, m transistor areas are arranged in a matrix or in a mosaic, and ineach transistor area, transistor elements Qi5, Qi6, Qi7 and Qi8 (i=1, 2,. . . , and m) are arranged so that the transistor elements Qi5 and Qi8are symmetrical about a center point Oi and the transistor elements Qi6and Qi7 are arranged, in a direction perpendicular to a direction inwhich the above transistor elements Qi5 and Qi8 are arranged, so as tobe symmetrical about the center point Oi, as shown in FIG. 4.

According to this embodiment, the variation of the electriccharacteristics of the current mirror transistors Qc and Qd can bereduced, so that a desired current ratio can be obtained in collectorsof the current mirror transistors Qc and Qd. Thus, a characteristic ofthe differential amplifier can be further improved.

In the above embodiment, the numbers n and m can be respectively set atvalues in accordance with desired electrical characteristic of thedifferential amplifier. In addition, the differential pair transistorsQa and Qb and the current mirror transistors Qc and Qd may be alsoformed of MOS transistor elements instead of bipolar transistorelements. In this case, the gate, source and drain respectivelycorrespond to the base, emitter and collector. In general, the offsetvoltage of the differential amplifier formed of the MOS transistors isgreater than that of the differential amplifier formed of the bipolartransistors. Thus, the present invention is effective in thedifferential amplifier formed of the MOS transistors. The differentialamplifier is formed of the MOS transistor elements, for example, asshown in FIG. 6.

Furthermore, the transistors in semiconductor device may be multiemittertransistors, multicollector transistors, multisource transistors, ormultidrain transistors.

The present invention is not limited to the aforementioned embodiments,and variations and modifications may be made without departing from thescope of the claimed invention.

What is claimed is:
 1. A semiconductor device comprising:a plurality ofgroups of transistor elements which are formed on a single semiconductorchip in a matrix of rows and columns, each group having a first pair oftransistor elements which are arranged so as to be symmetrical about apoint and a second pair of transistor elements which are arranged, in adirection perpendicular to a direction in which said first pair oftransistor elements are arranged, so as to be symmetrical about thepoint; means for connecting said first pair of transistor elements inall said plurality of groups in parallel so that a first transistor forsaid device is formed of said first pairs of transistor elements suchthat no two parallel connected transistor elements are in juxtaposition;and means for connecting said second pair of transistor elements in allsaid plurality of groups in parallel so that a second transistor forsaid device is formed of said second pairs of transistor elements suchthat no two parallel connected transistor elements are in juxtaposition,said first transistor and said second transistor being connected to forma transistor pair.
 2. The semiconductor device as claimed in claim 1,wherein said semiconductor device is a differential amplifier havingdifferential input transistors formed of said first transistor and saidsecond transistor.
 3. The semiconductor device as claimed in claim 1,wherein said semiconductor device is a differential amplifier havingdifferential input transistors and a current mirror circuit formed ofsaid first transistor and said second transistor, said current mirrorcircuit being connected to said differential transistors as a loadthereof.
 4. The semiconductor device as claimed in claim 1, wherein eachof said transistor elements is a bipolar transistor.
 5. Thesemiconductor device as claimed in claim 1, wherein each of saidtransistor elements is a MOS transistor.
 6. The semiconductor device asclaimed in claim 2, wherein said semiconductor device is a differentialamplifier having a current mirror circuit connected to said differentialinput transistors, and wherein said current mirror circuit is formed ofsecond and third transistors formed of a plurality of groups oftransistor elements in the same manner as said first and secondtransistors.